1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to central processing subsystems that are implemented using microprogramming techniques. By providing a plurality of control stores that are accessed by the same microinstruction at different time periods, simplifications in implementation of the central processing subsystem can be achieved.
2. Description of the Related Art
Referring to FIG. 1, a typical data processing system is shown. The data processing system includes at least one central processing unit or subsystem 10 (and 11), at least one input/output unit or subsystem 13 and 14), a main memory unit or subsystem 15 and a system bus 19 coupling the plurality of units or subsystems. The central processing unit(s) 10 (and 11) can manipulate groups of logic signals according to a sequence of instructions in a program or program stored in software and/or firmware. Typically the logic signal groups and the program itself are stored, at least during program execution, in the main memory unit 15. The input/output unit(s) 13 (and 14) can provide an interface between the data processing system and terminal units, mass storage units, communication units and other units requiring coupling to the data processing system. A console unit 12 can be coupled to the central processing unit(s) 10 (and 11) in order to initialize the data processing system, to control test and diagnostic procedures, and to be used as a termianl unit when the system is in operation. The system bus, 19 by providing a coupling between data processing system subsystems, provides a convenient technique for altering the configuration of the data processing system to accommodate a variety of processing requirements. The present invention relates to the execution of instructions by the central processing unit(s) 10 (and 11).
In a data processing system, such as is illustrated in FIG. 1, the actual manipulation of data signal groups takes place under the control of a group of related instructions that is generally called a program. These instructions are executed in a sequence. Referring next to FIG. 2a, the execution of a series of instructions according to the related art is illustrated. During a first time interval, T.sub.o, the instruction #1 21 is executed by a central processing unit subsystem. After the first instruction 21, is executed, a next instruction #2 22 in the sequence is executed by the central processing unit subsystem during the second time interval T.sub.o. Upon completion of instruction #2, 22 the data processing unit executes instruction #3 23 during a third time interval T.sub.o. In order to maintain an orderly execution of instructions, the interval for the execution of any instruction by the data processing unit requires a predetermined period of time. If the execution time for an instruction can have a variable length, complex apparatus must then be included in the central processing unit to coordinate the exchange of data signal groups between the groups of logic components within the central processing unit and between the central processing unit and the other subsystems of the data processing system. Thus, the period for execution of the three instructions will generally be three times the basic time period T.sub.o. It will be clear that the basic time interval must be of sufficient duration to permit the execution of the lengthiest instruction in the instruction set.
In order to provide for faster execution of instructions by the central processing unit, a technique for dividing the execution of an instruction, generally referred to as a macroinstruction, into the execution of at least one microinstruction has been devised. Each microinstruction is, in turn, divided into a group of microinstruction segments, each segment being executed sequentially by the central processing unit. By organizing the apparatus executing the microinstruction segments in an appropriate manner, the execution of the microinstructions can be performed in an overlapping manner. This technique is referred to as "pipelining" the execution of an instruction set. While the execution of each segmented microinstruction 2n' can (althougn not necessarily) take a longer period of time than is required for the execution of a nonsegmented microinstruction 2n, because of the additional apparatus required for the division of the microinstruction into the microinstruction segments, an instruction stream can be executed faster than is possible for nonsegmented microinstruction 2.sub.n. In FIG. 2b, the division of an microinstruction 2n' into a plurality of segments A.sub.n, B.sub.n, C.sub.n and D.sub.n is shown. It will be understood that each segment relates to a separate and independently operating group of components in the central processing unit. Registers and gates, according to principals well-known in the art of data processing system design, separate the operation of component group executing a particular microinstruction segment. The subinterval, t.sub.o, for each segment A.sub.n, B.sub.n, C.sub.n and D.sub.n must be of sufficient period of time to permit the execution of all possible segments in each apparatus group.
Referring next to FIG. 2c, the resulting increase in the rate of execution of a sequence of microinstrucitons possible, through the use of pipelining techniques, is illustrated. Instruction #1 21 is now completed in the new (and possibly longer) time period of T'.sub.o equals m times t.sub.o, where t.sub.o is the subinterval required for the execution of each microinstruction segment A.sub.n, B.sub.n, C.sub.n and D.sub.n and where m is the number of microinstruction segments required for the execution of each microinstruction. The next microinstruction in the sequence, microinstruction #2 22, begins an interval t.sub.o after the beginning of microinstruction #1 21. The third microinstruction in the sequence, microinstruction #3 23, then begins an interval t.sub.o thereafter. Each microinstruction can take the increased amount of time for the execution. However, once the initial interval for the completion of the first microinstruction has passed, a microinstruction can be completed after each interval t.sub.o. Thus, for a sequence of microinstructions, the execution of the sequence can be accelerated even through execution of the individual microinstruction can take an increased length of time.
Referring next to FIG. 3a, an organization for a central processing unit 10 implementing the pipelined execution of an microinstruction sequence is shown. The central processing unit 10 is divided into an instruction subunit 31 and associated control unit 32, an execution subunit 33 and a cache (or local) memory subunit 34. The cache memory subunit 34 is coupled to the system bus 19 and exchanges groups of logic signals with the other subsystems of the data processing system by means of the system bus 19 under control of the control unit 32. The execution subunit 33, again under control of the control unit 32, performs the manipulation of the data signal groups that is defined by the instructions being executed. The instruction subunit 31 receives the macroinstructions to be executed and reformats the instructions in a manner that can be used to control the operation of the central processing unit 10. The signals corresponding to the macroinstructions are applied to a random access memory or the logic apparatus in the control unit 32. The location of the random access memory in control unit 32, addressed by the macroinstruction signals, contains an address. This address is then applied to a control store within control unit 32, the control store being implemented by an addressable memory. The output signals from the control store are referred to as the microinstructions and are logic signals that are applied to the logic elements of the central processing processing system. The signals provided by the microinstructions control the operation of central procesing unit. The signals from the microinstructions are arranged in groups called micro-orders, and each micro-order can be used to control a portion of the central processing unit, for example, the execution of a microinstruction segment by the execution subunit 32.
Referring to the simplified division of the data processing unit shown in FIG. 3a and for purposes of illustrating the invention, the length of time for each unit of the central processing unit 10 to complete its portion of an execution of an instruction will be taken to be equal. Thus, for an instruction to be executed by the central processing unit 10, the execution of a set of instructions is illustrated in FIG. 2c. It will be understood that use of the term "cycles(s)" herein shall not be limited to mean one full clock cycle of the central processing unit 10. The time intervals in FIGS. 3b, 4a and 4b may represent either full or partial cycles of the central processing unit, depending on considerations of logic design that are well understood by those of ordinary skill in the art. Referring to both FIGS. 2c and 3b, the first instruction #1 21 will be processed by instruction subunit 31 during a first interval t.sub.o. During second interval t.sub.o, the execution subunit 33 of the data processing unit can be processing the first instruction #1 21, while the instruction subunit 31 of the central processing system 10 can be processing the second instruction #2 22. During the third interval t.sub.o, the cache memory unit 34 can be processing instructin #1 21, the execution unit 33 can be processing instruction #2 22, and the instruction unit 31 can be processing instruction #3 23. This three level pipeline, with concurrent processing in the cache memory subunit 34, the execution subunit 33 and the instruction subunit 31, can continue as long as instructions are entered into the instruction subunit 31 or as long as addresses are provided by a microbranch and sequencer logic unit 405 (shown in FIG. 4b).
It will be clear that the division of the data processing unit into the indicated functional units is, in general, not sufficient to provide an operable pipeline configuration. Each of the functional subunits 31, 32, 33, and 34 described above can require a plurality of subunits to complete each requisite operation to complete the execution of each instruction. With division of the central processing unit 10 into a multiplicity of subunits executing a given microinstruction in a sequential manner, the groups of signals, sometimes referred to as micro-orders, controlling the individual units must be systematically delayed to coordinate the micro-orders with the flow of the signal groups, being processed, through the subunits of the central processing unit 10.
Referring to FIG. 3b, a control unit 32' for use in delaying the issuance of miro-orders is shown. As seen in FIG. 3b, a macroinstruction is extracted from a unit such as an instruction buffer (not shown) in instruction subunit 31 (refer to FIG. 3a), and applied to a decoder random access memory 50. During time T.sub.3, the output of random access memory 50, an address of the first of a set of microinstructions for performing the macroinstruction, is applied to control store 60 through a temporary storage element such as a latch 70 and buffer 80. (It will be understood that in the following description the use of the term "latch" or "buffer" shall not be limiting. Any temporary storage element, such as a flip-flop circuit or trigger circuit may be substituted.) Control store 60 generates the associated set of micro-orders, which are then applied to latch 62.
Latch 62 is divided into three sections to accommodate the three level pipline illustrated in FIG. 2c. Thus, during time period T.sub.4, one of its three sets of logic signal groups stored in latch 62 are applied as micro-orders to an associated subunit (S) of the central processing unit, while the remaining two sets are applied to latch 64. During time period T.sub.5, one of the remaining sets of micro-orders is applied to an associated subunit (S) of the central processing unit and stores the last set of logic signal groups in latch 68. Then, during time T.sub.6, the last set of micro-orders from latch 68 is applied to the associated subunit.
As can be seen, as the complexity of the central processing unit increases, the complexity of the control unit 32' increases. The microinstructions become increasingly large and unwieldy and, consequently, the numbers and the sizes of latches in control unit 32 (or 32') increase. A need has therefore been felt for a technique that would provide more manageable microinstruction control and reduce the problems involved in the timely application of the micro-orders to the subunits of the centeral processing unit 10.